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AN07-00180-3E
Table 5-2 Description of the entire CAN communication control registers and setting values
Register name
CTRLR0_Test
CTRLR0_CCE
CTRLR0_DAR
CTRLR0_EIE
CTRLR0_SIE
CTRLR0_IE
CTRLR0_Init
BTR0
TESTR0_Rx
TESTR0_Tx1
TESTR0_Tx0
TESTR0_LBack
TESTR0_Silent
TESTR0_Basic
BRPER0_BRPE
Setting value [function]
0 [normal operation]
1 [write enable]
0 [automatic retransmit enable]
0 [code setting disable]
0 [code setting disable]
0 [interrupt disable]
1 [initialization]
0x2B43 [250 Kbps]
0 [dominant]
0 [normal operation]
0 ↑
0 [loopback mode disable]
0 [silent mode disable]
0 [basic mode disable]
0 [value added to BTR0]
Description
Test mode enable bit
Bit timing register write enable bit
Automatic retransmit prohibit bit
Error interrupt code enable bit
Status interrupt code enable bit
Interrupt enable bit
Initialization bit
CAN communication speed
RXO pin monitor bit
TXO pin control bits
Loopback mode
Silent mode
Basic mode
Baud rate prescaler extension bit
The registers used for CAN communication message handling on the microcontroller are APIs of the
CAN driver in the sample software, so descriptions of the following registers are omitted. For more
information of the registers, refer to the microcontroller hardware manual.
■ Message interface registers
- IFx command request register (IFxCREQ)
- IFx command mask register (IFxCMSK)
- IFx mask register 1, 2 (IFxMSK1, IFxMSK2)
- IFx arbitration register 1, 2 (IFxARB1, IFxARB2)
- IFx message control register (IFxMCTR)
- IFx data register A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2)
■ Message handler registers
- CAN transmit request register 1, 2 (TREQR1, TREQR2)
- CAN data update register 1, 2 (NEWDT1, NEWDT2)
- CAN interrupt pending register 1, 2 (INTPND1, INTPND2)
- CAN message enable register 1, 2 (MSGVAL1, MSGVAL2)
- 94 -
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